DPSB: Dual port shared buffer mechanism for efficient buffer utilization in Network on Chip routers

Nowadays, Multiprocessor System on Chip (MPSoC) system performance is often limited by the growing interconnection between processing elements. Network on Chip (NoC) as an interconnection platform is becoming a promising solution due to its scalability and reusability over conventional bus-based interconnection. An NoC router is the vital component in the NoC architecture. Efficient router leads to an efficient NoC platform and subsequently provides better system performance. In this paper, we propose a new shared buffer based router architecture employing dual buffers. We show that the proposed architecture has an advantage in its increased buffer utilization leading to an improved throughput and reduced latency. The experiments show that the proposed architecture improves the NoC´s throughput and latency compared with a conventional architecture with little overhead in the control logic.