Area efficient half row pipelined layered LDPC decoder for gigabit wireless communications

This work presents an area efficient half row partially parallel pipelined LDPC decoder architecture for IEEE 802.11ad standard. It provides better area and throughput tradeoff by overcoming the low throughput bottleneck in conventional half row decoders and high complexity bottleneck in fully parallel decoders. The proposed architecture is implemented using 40-nm CMOS technology. The proposed half-row pipelined decoder achieves the maximum required throughput of 8.4 Gb/s for IEEE 802.11ad standard and shows superior area efficiency compared to previous works.