A low jitter PLL design using active loop filter and low-dropout regulator for supply regulation

This paper presents low power and low jitter phase locked loop (PLL) design using supply regulation and active loop filter (ALF) on 110nm CMOS technology and with 1V supply voltage. The supply voltage is regulated by low-dropout (LDO) regulator. The ALF filters high frequency noise of the VCO control voltage. The LDO regulator provides 0.8V output, -83 dB PSRR with PLL load, 0.578mW power consumption, and 99.8% current efficiency with 40mA load current. The jitter of the PLL without and with LDO regulator is 44.9ps and 4.6ps, respectively.