A 10-b 10MS/s SAR ADC with power and accuracy control of the comparator

This paper proposes a 10-b 10MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) structure using Vcm based capacitive digital-to-analog (CDAC). In the proposed capacitive DAC, switching is always straightforward and the MSB is decided without any switching energy. The input is sampled at the bottom plate of the CDAC as it provides better linearity. Comparator applies adaptive power control to reduce the power consumption. For further power reduction, the accuracy of the comparator for coarse and fine bits are different and the reconfigurable structure has been applied. A prototype ADC was implemented in CMOS 0.18μm technology. This structure consumed 330μW and achieved 58.9-dB SNDR and 66.5-dB SFDR at 10MS/s under a 1.8-V supply. The figure of merit (FOM) was 58fJ/conversion-step.