A source-follower with bias current regulator for enhanced linearity

This paper proposes a highly linear source follower (S.F) circuit aiming for the front-end buffer of data convertors. The linearity is systematically improved by maintaining an invariant voltage drop between gate and source nodes of an MOSFET placing a current regulator in series with the source follower. Simulation results using 65nm CMOS technology conceal the linearity enhancement from 0.860 to 0.967 without degrading the bandwidth. The source-follower dissipates 0.5mW from a 1.2 V supply and input swing range of 0.5 Vpp.