FPGA implementation of HOG based pedestrian detector

We present a FPGA implementation of a pedestrian detector that can process VGA video at a frame rate of 30-40 frames per second in real time. The architecture implements an offline trained boosted detector in an attentional cascade. The cascade evaluates each frame using histogram of gradient (HOG) features in the LUV color space. Pedestrian targets are identified at 27 scales. Feature aggregation allows the design to operate on fewer candidate windows that would normally be required for a 640×480 frame. The design is implemented on a Xilinx Zynq FPGA using a FMC for video input. Video frames are buffered in off-chip DRAM and then streamed through a processing pipeline. The pipeline performs color space conversion, frame rescaling, HOG feature extraction, and candidate evaluation in a sliding window. The candidate evaluation is parallelized to evaluate two windows at a time. The entire pipeline is parallelized to evaluate multiple scales per frame.