A DC-50 GHz SPDT switch with maximum insertion loss of 1.9 dB in a commercial 0.13-?m SOI technology

In this paper, a low insertion loss, high isolation, ultra wideband (DC to 50 GHz) single-pole double-throw (SPDT) switch using 0.13 μm SOI technology is presented. The switch is designed by using a series-shunt configuration with input and output matching networks. The channel length and gate bias impacts on switch performance are studied. It is found that the transistor channel length has dominant effects on both the insertion loss and isolation. The measured insertion loss of the SPDT with 0.13 μm channel length transistor is less than 1.9 dB up to 50 GHz, while the isolation is better than 27 dB. Measured P1dB for SPDT switch is larger than 12 dBm. The active chip area of designed SPDT switch is only 0.21 × 0.19 mm².