A 6-bit 320-MS/s 2-bit/cycle SAR ADC with tri-level charge redistribution

In this paper, a 6-bit 320-MS/s successive approximation register analog-to-digital converter (SAR ADC) is presented. The 2-bit/cycle technique and tri-level based charge redistribution technique are utilized to achieve high conversion rate and reduce the hardware cost. The proposed ADC is designed and implemented in a 65-nm CMOS process. Simulation results show that it accomplishes 48.52-dB SFDR, 37.30-dB SNDR and 5.90 ENOB for a 9.06-MHz 0.6-Vpp sinusoidal input signal at 320-MS/s sampling rate. With a 151.20MHz input frequency, the SFDR and SNDR maintains above 48dB and 34dB respectively. The ADC has a total power consumption of 9.81mW at 320MS/s, corresponding to a figure of merit (FOM) of 479fJ/step.