Low power design for on-chip networking processing system

Recently, network energy consumption and carbon emission statistics show an alarming and growing trend. Such high power requirement can be mainly due to networking hardwares (primarily router processors) designed to operate at maximum capacity with constant and highest energy consumption, independent of the network traffic load. However, recent developments of green network on-chip systems using power proportional technologies suggest the chance to adapt their performance and energy consumption to meet actual workload and operational requirements. In such a scenario, this paper aims at implementing a low power networking processing system by on-chip Dynamic Frequency Scaling (DFS) and Physical Port Switch (PPS), and proposing a control scheme to minimise the number of clock frequency switches that maximises energy saving with negligible Quality of Service(QoS) loss overhead.