Title :
A 9-bit, 110-MS/s pipelined-SAR ADC using time-interleaved technique with shared comparator
Author :
Taehoon Kim;Sunkwon Kim;Jong-Kwan Woo;Hyongmin Lee;Suhwan Kim
Author_Institution :
Electrical and Computer Engineering and Inter-university Semiconductor Research Center Seoul National University, Seoul, 151-744, Korea
Abstract :
A 9-bit 110-MS/s pipelined-SAR ADC is proposed. To alleviate the design tradeoff between conversion rate and power consumption, the design adopts a voltage-mode open-loop amplifier and a time-interleaved SAR architecture with comparator sharing. The ADC simulated in a 65-nm CMOS technology achieves an ENOB of 8.63 bits near the Nyquist input frequency at the sampling rate of 110MS/s. The power consumption is 7.9mW, resulting in 181.3fJ/conversion-step of Figure of Merit (FoM).
Keywords :
"Capacitors","Power demand","CMOS integrated circuits","Clocks","Solid state circuits","CMOS technology","Linearity"
Conference_Titel :
System-on-Chip Conference (SOCC), 2015 28th IEEE International
Electronic_ISBN :
2164-1706
DOI :
10.1109/SOCC.2015.7406934
