A scan segmentation architecture for power controllability and reduction

With the chip size entering the micro-nano level, the increasing power consumption during the chip testing process becomes the bottleneck of chip production and testing. Prior work has been mainly focused on reducing power dissipation in either shift cycle or capture cycle, however, there has been limited work on reducing the peak power in both shift and capture cycles at the same time. Moreover, there has been no work on the problem of capture power controllability. This paper proposes a new power-aware scan segment architecture, which can accurately control the power of shift and capture cycles at the same time with small area overhead. Meanwhile, we devise sophisticated algorithms of dependency checking and scan segments partitioning, which can directly reduce simultaneously switching activity of flip-flops by iterative optimizing scan segments grouping. To the best of our knowledge, this paper is the first of its kind to study the problem of power controllability considering both structure dependency and clock trees´ impact. Extensive experiments have been performed on reference circuit ISCAS89 and IWLS2005 to verify the effectiveness of the proposed architecture.