Title :
Evaluation of energy-efficient latch circuits with hybrid tunneling FET and FinFET devices for ultra-low-voltage applications
Author :
Tse-Ching Wu;Chien-Ju Chen;Yin-Nien Chen;Vita Pi-Ho Hu;Pin Su;Ching-Te Chuang
Author_Institution :
Department of Electronics Engineering & Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan
Abstract :
In this paper, we investigate the hybrid TFET-FinFET latch circuits and compare the clock-to-Q delay, dynamic energy, leakage power and energy-delay product (EDP) with all FinFET and all TFET implementations in near-threshold region. We use atomistic 3D TCAD mixed-mode simulations for transistor characteristics and HSPICE circuit simulations with look-up table based Verilog-A models calibrated with TCAD simulation results. Four types of latch circuits are evaluated, including standard clocked CMOS latch (SCCL), low-voltage C2MOS latch (LVCL), master-slave transmission-gate latch pair (MTLP) and pulse-triggered latch (PTL). In the hybrid design, TFETs are used for critical path to reduce the clock-to-Q delay, and FinFETs are used for the rest of the circuits to reduce the power consumption. The hybrid latch circuits are shown to offer comparable or better clock-to-Q delays while exhibiting superior EDP compared with all TFET implementations. Among the four types of latch circuits, the hybrid TFET-FinFET LVCL exhibits the most significant clock-to-Q delay and EDP improvements at low operating voltage (<; 0.30V). With work function variation (WFV) and fin line-edge roughness (LER), the hybrid LVCL exhibits superior and comparable EDP variability compared with all FinFET and all TFET implementations at 0.25V.
Keywords :
"FinFETs","Latches","Hybrid power systems","Delays","Integrated circuit modeling","Hardware design languages"
Conference_Titel :
System-on-Chip Conference (SOCC), 2015 28th IEEE International
Electronic_ISBN :
2164-1706
DOI :
10.1109/SOCC.2015.7406978