• DocumentCode
    3746140
  • Title

    ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

  • Author

    Chia-Tsen Dai;Ming-Dou Ker

  • Author_Institution
    Institute of Electronics, National Chiao-Tung University, Hsinchu, Taiwan
  • fYear
    2015
  • Firstpage
    380
  • Lastpage
    383
  • Abstract
    For high-voltage (HV) application, an on-chip ESD protection solution has been proposed in a 0.25-μm HV BCD process by using low-voltage (LV) p-type devices with the stacked configuration. Experimental results in silicon chip have verified that the proposed design can successfully protect the 60-V pins of a battery-monitoring IC against over 8-kV human-body-mode (HBM) ESD stress.
  • Keywords
    "Electrostatic discharges","Stress","MOS devices","Current measurement","Robustness","Pins","Integrated circuits"
  • Publisher
    ieee
  • Conference_Titel
    System-on-Chip Conference (SOCC), 2015 28th IEEE International
  • Electronic_ISBN
    2164-1706
  • Type

    conf

  • DOI
    10.1109/SOCC.2015.7406987
  • Filename
    7406987
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3746140