Title :
Simulation model to control risk levels on process equipment through metrology in semiconductor manufacturing
Author :
Alejandro Send?n;St?phane Dauz?re-P?r?s;Jacques Pinaton
Author_Institution :
Ecole des Mines de Saint-Etienne, Department of Manufacturing Sciences and Logistics, CMP, Site Georges Charpak, CNRS UMR 6158 LIMOS, 880 avenue de Mimet, F-13541 Gardanne, FRANCE
Abstract :
This paper first presents a simulation model implemented to study a specific workcenter in semiconductor manufacturing facilities (fabs) with the objective of controlling the risk on process equipment. The different components of the model, its inputs and its outputs, that led us to propose improvements in the workcenter, are explained. The risk evaluated in this study is the exposure level in the number of wafers on a process tool since the latest control performed for this tool, based on an indicator called Wafer at Risk (W@R). Our analysis shows that measures should be better managed to avoid lack of control and that an appropriate qualification strategy is required.
Conference_Titel :
Winter Simulation Conference (WSC), 2015
Electronic_ISBN :
1558-4305
DOI :
10.1109/WSC.2015.7408397