DocumentCode
3748102
Title
A methodology to predict the impact of wafer level chip scale package stress on high-precision circuits
Author
R. van Dalen;H. P. Tuinhout;M. Stoutjesdijk;J. van Zwol;J. J. M. Zaal;J. H. J. Janssen;F. H. M. Swartjes;P. A. M. Bastiaansen;M. C. Lammers;L. Brusamarello;M. Stekelenburg
Author_Institution
NXP Semiconductors, The Netherlands
fYear
2015
Abstract
A methodology is presented that allows quantitative prediction of the impact of WLCSP induced mechanical stress on high precision mixed-signal ICs. The simulation flow was tuned using high-resolution experimental variability data measured on dedicated test chips. The methodology is exemplified with an on-chip oscillator circuit suffering from WLCSP stress induced variability.
Keywords
"Stress","Integrated circuit modeling","Resistors","Sensitivity","Semiconductor device measurement","Oscillators","Temperature measurement"
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN
2156-017X
Type
conf
DOI
10.1109/IEDM.2015.7409646
Filename
7409646
Link To Document