DocumentCode :
3748109
Title :
A robust wafer thinning down to 2.6-?m for bumpless interconnects and DRAM WOW applications
Author :
Y. S. Kim;S. Kodama;Y Mizushima;T. Nakamura;N. Maeda;K. Fujimoto;A. Kawai;K. Arai;T. Ohba
Author_Institution :
WOW Alliance, Tokyo Institute of Technology, 4259 Nagatsuda, Midori-ku, Yokohama 226-8503, Japan
fYear :
2015
Abstract :
An ultra-thinning down to 2.6-μm with and without Cu contamination at 1013 atoms/cm2 using 300-mm wafer proven by 2Gb DRAM has been developed for the first time. The impact of Si thickness and Cu contamination at wafer backside for DRAM yield including retention characteristics is described. Thickness uniformity for all wafers after thinning was below 2-μm within 300-mm wafer. A degradation in terms of retention characteristics occurred after thinning down to 2.6-μm while no degradation after thinning down to 5.6-μm for both wafer and package level test were found.
Keywords :
"Silicon","Random access memory","Contamination","Degradation","Abrasives","Capacitance","Pollution measurement"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409653
Filename :
7409653
Link To Document :
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