Experimental study on BTI variation impacts in SRAM based on high-k/metal gate FinFET: From transistor level Vth mismatch, cell level SNM to product level Vmin

Aging induced variability has been shaving away the design margins in advanced SRAM which may become more serious with highly scaled process node. This paper provides a systematical study of the BTI variation impacts in FinFET SRAM based on 14nm 128Mbit SRAM, including the characterization from transistor and cell level to product. For transistor level, despite the effective process optimization for BTI shifts, SRAM transistor Vth mismatch shows non-negligible increase after aging due to the intrinsic Sqrt(1/WL) BTI variability trend as time=0 variations. For cell level, BTI distribution is found to be the dominant factor comparing with the circuit level parameters such as Vdd or inverter (PU/PD) ratio in terms of read SNM shifts after aging. An empirical model of EOL SNM is further proposed for the circuit level quick evaluation and HTOL fail prevention. For product level, the FBC (Failure Bit Count) slope from cell-to-cell variation and Vmin distribution from chip-to-chip variation also show non-negligible impacts due to BTI variability. The results indicate that besides the process optimization for BTI mean shifts, reliability aware circuit design is necessity to consider intrinsic BTI variation increase with transistor scaling down.