DocumentCode :
3748140
Title :
A computational study of van der Waals tunnel transistors: Fundamental aspects and design challenges
Author :
Jiang Cao;Demetrio Logoteta;Sibel ?zkaya;Blanca Biel;Alessandro Cresti;Marco Pala;David Esseni
Author_Institution :
IMEP-LAHC, Grenoble-INP, 3 Parvis Louis N?el, 38016 Grenoble, France
fYear :
2015
Abstract :
We propose a model Hamiltonian for van der Waals tunnel transistors relying on a few physical parameters that we calibrate against DFT band structure calculations. This approach allowed us to develop a fully three-dimensional (3-D) NEGF based simulator and to investigate fundamental and design aspects related to van der Waals tunnel transistors, such as: (a) area and edge tunneling components, and scaling with device area; (b) impact of top gate alignment and back-oxide thickness on the device performance; (c) influence of inelastic phonon scattering on the device operation and sub-threshold swing; (d) benchmarking of switching energy and delay.
Keywords :
"Phonons","Logic gates","Tunneling","Discrete Fourier transforms","Scattering"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409684
Filename :
7409684
Link To Document :
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