DocumentCode :
3748159
Title :
Novel wafer-scale uniform layer-by-layer etching technology for line edge roughness reduction and surface flattening of 3D Ge channels
Author :
Y. Morita;T. Maeda;H. Ota;W. Mizubayashi;S. O´uchi;M. Masahara;T. Matsukawa;K. Endo
Author_Institution :
National Institute of Advanced Industrial Science and Technology (AIST) 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan
fYear :
2015
Abstract :
We have developed a novel wafer-scale uniform layer-by-layer etching technology based on the etching reaction of oxygen molecules with Ge surfaces. The advantages of this etching technology are as follows. (1) Layer-by-layer etching can be achieved, yielding an atomically flat step-terrace surface. (2) Because of the very small activation energy (<;0.1 eV) of the etching reaction, this technology is free from etch rate variation caused by temperature inhomogeneity over large wafers. (3) No plasma damage occurs as a result of O2 molecule reactions with anisotropic etching. These features are applicable to the fabrication of three-dimensional Ge channels.
Keywords :
"Etching","Silicon","Rough surfaces","Surface roughness","Plasma temperature","Surface morphology"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409703
Filename :
7409703
Link To Document :
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