• DocumentCode
    3748179
  • Title

    Gate/Source overlapped heterojunction tunnel FET for non-Boolean associative processing with plasticity

  • Author

    A. R. Trivedi;R. Pandey;H. Liu;S. Datta;S. Mukhopadhyay

  • Author_Institution
    Georgia Institute of Technology, Atlanta, GA
  • fYear
    2015
  • Abstract
    This work presents a gate/source-overlapped HTFET (SO-HTFET) with Gaussian IDS-VGS, utilized as a single transistor distance computing cell (DCC) for associative processing (AP). With much simplified DCC, inter-cell coupling, and peripherals, SO-HTFET-based AP shows 250× lower power, much higher cell density, and performance than digital CMOS-based Boolean AP.
  • Keywords
    "Logic gates","Transistors","Programming","Computer architecture","Microprocessors","Tunneling","Training"
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2015 IEEE International
  • Electronic_ISBN
    2156-017X
  • Type

    conf

  • DOI
    10.1109/IEDM.2015.7409723
  • Filename
    7409723
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3748179