DocumentCode :
3748214
Title :
Sub-60mV-swing negative-capacitance FinFET without hysteresis
Author :
Kai-Shin Li;Pin-Guang Chen;Tung-Yan Lai;Chang-Hsien Lin;Cheng-Chih Cheng;Chun-Chi Chen;Yun-Jie Wei;Yun-Fang Hou;Ming-Han Liao;Min-Hung Lee;Min-Cheng Chen;Jia-Min Sheih;Wen-Kuan Yeh;Fu-Liang Yang;Sayeef Salahuddin;Chenming Hu
Author_Institution :
National Nano Device Laboratories, National Applied Research Laboratories, Hsinchu, Taiwan
fYear :
2015
Abstract :
In this work, we report the first Negative-Capacitance FinFET. ALD Hf042Zr058O2 is added on top of the FinFET´s gate stack. The test devices have a floating internal gate that can be electrically probed. Direct measurement found the small-signal voltage amplified by 1.6X maximum at the internal gate in agreement with the improvement of the subthreshold swing (from 87 to 55mV/decade). ION increased by >25% for the IOFF. For the first time, we demonstrate that raising HfZrO2 ferroelectricity, by annealing at higher temperature, reduces and eliminates IV hysteresis and increases the voltage gain. These discoveries will guide future theoretical and experimental work.
Keywords :
"Logic gates","FinFETs","Annealing","Voltage measurement","Temperature measurement","Hysteresis","CMOS integrated circuits"
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
Type :
conf
DOI :
10.1109/IEDM.2015.7409760
Filename :
7409760
Link To Document :
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