Title :
Systematic optimization of 1 Gbit perpendicular magnetic tunnel junction arrays for 28 nm embedded STT-MRAM and beyond
Author :
C. Park;J. J. Kan;C. Ching;J. Ahn;L. Xue;R. Wang;A. Kontos;S. Liang;M. Bangar;H. Chen;S. Hassan;M. Gottwald;X. Zhu;M. Pakala;S. H. Kang
Author_Institution :
Qualcomm Technologies, Inc., San Diego, California 92121, USA
Abstract :
This paper demonstrates the co-optimization of all critical device parameters of perpendicular magnetic tunnel junctions (pMTJ) in 1 Gbit arrays with an equivalent bitcell size of 22 F2 at the 28 nm logic node for embedded STT-MRAM. Through thin-film tuning and advanced etching of sub-50 nm (diameter) pMTJ, high device performance and reliability were achieved simultaneously, including TMR = 150 %, Hc > 1350 Oe, Heff <; 100 Oe, Δ = 85, Ic (35 ns) = 94 μA, Vbreakdown = 1.5 V, and high endurance (> 1012 write cycles). Reliable switching with small temporal variations (<; 5 %) was obtained down to 10 ns. In addition, tunnel barrier integrity and high temperature device characteristics were investigated in order to ensure reliable STT-MRAM operation.
Keywords :
"Switches","Tunneling magnetoresistance","Reliability","Temperature","Magnetic tunneling","Annealing","Films"
Conference_Titel :
Electron Devices Meeting (IEDM), 2015 IEEE International
Electronic_ISBN :
2156-017X
DOI :
10.1109/IEDM.2015.7409771