Title :
A Clock-less 8-bit folding A/D converter
Author :
S.A. Rodrigues;J.I.C. Accioly;H. Aboushady;M.M. Lou?rat;D. R. Belfort;R.C.S. Freire
Author_Institution :
Electrical Engineering Coordination, Federal Institute of Education Science and Technology (IFPB), Jo?o Pessoa - Paraiba - Brazil
Abstract :
This paper presents a continuous-time 8-bit folding analog-to-digital converter. The clock-less architecture is composed of 8 identical stages with 1 bit/stage. The circuit is designed in a 350nm CMOS process with a supply voltage of 3.3V. Simulation results show that the 8-bit clock-less ADC can achieve a Signal-to-Noise and Distortion Ratio of 53dB. The ADC has a power consumption of 5.51mW. The proposed circuit is compared with a similar continuous-time 8-bit pipeline ADC with 1 bit/stage.
Keywords :
"Pipelines","Operational amplifiers","Analog-digital conversion","Quantization (signal)","Computer architecture","Clocks","Differential amplifiers"
Conference_Titel :
Circuits and Systems (LASCAS), 2010 First IEEE Latin American Symposium on
DOI :
10.1109/LASCAS.2010.7410131
