Title :
A fully integrated 65 nm CMOS cascode HSFDS PA dedicated to 802.11n application
Author :
Y. Luque;E. Kerherv?;N. Deltimple;D. Belot
Author_Institution :
University of Bordeaux, IMS laboratory, Talence cedex, France
Abstract :
This paper presents a 65nm CMOS-power amplifier (PA) designed for WiFi communications. The PA is based on a Half Stacked Folded Differential Structure (HSFDS) cascoded. The PA is designed for the WiFi 802.11n standard. The power amplifier provides 24.5 dBm output powers with 25% of power added efficiency (PAE) at 2.45 GHz. The linear gain is 15.5 dB and the compression point (OCP1) is 18.5 dBm. In order to meet the 802.11n requirements, the PA is linear until 16 dBm, which is the maximum output power required by this standard.
Keywords :
"CMOS integrated circuits","CMOS technology","Layout","Power amplifiers","Linearity","Power generation","Simulation"
Conference_Titel :
Circuits and Systems (LASCAS), 2010 First IEEE Latin American Symposium on
DOI :
10.1109/LASCAS.2010.7410220
