A MIPS-based ASIP to accelerate the inverse Hadamard tranform for H.264/AVC video coding

This paper presents a set of modifications in the 5-stage pipelined MIPS processor aiming at the acceleration of the 4×4 inverse Hadamard transform execution for H.264/AVC video coding standard. New functional units, registers and control signals were implemented, requiring the addition of three new special instructions for the Hadamard transform computation. The introduction of application-specific instructions and hardware acceleration resulted in 10 times reduction in the number of cycles required for the total computation of the transform kernel, compared to the original architecture. The amount of hardware resources used by the circuit including the transform co-processor increased only by 54.43%, and the maximum frequency of the application-specific instruction set processor (ASIP) [10] circuit remained unchanged.