DocumentCode
3749204
Title
Analysis of ring topology for NoC architecture
Author
Avinash Kamath;Gaurangi Saxena;Basavaraj Talawar
Author_Institution
Department of Computer Science and Engineering, National Institute of Technology Karnataka, Surathkal, India
fYear
2015
Firstpage
381
Lastpage
388
Abstract
In recent years, Network on Chips (NoCs) have provided an efficient solution for interconnecting various heterogeneous intellectual properties (IPs) on a System on Chip (SoC) in an efficient, flexible and scalable manner. Virtual channels in the buffers associated with the core helps in introducing the parallelism between the packets as well as in improving the performance of the network. However, allocating a uniform size of the buffer to these channels is not always suitable. The network efficiency can be improved by allocating the buffer variably based on the traffic patterns and the node requirements. In this paper, we use ring topology as an underlying architecture for the NoC. The percentage of packet drops has been used as a parameter for comparing the performance of different architectures. Through the results of the simulations carried out in SystemC, we illustrate the impact of including virtual channels and variable buffers on the network performance. As per our results, we observed that varied buffer allocation led to a better performance and fairness in the network as compared to that of the uniform allocation.
Keywords
"Registers","Computer architecture","Topology","Network topology","Resource management","Routing","Wires"
Publisher
ieee
Conference_Titel
Computing and Network Communications (CoCoNet), 2015 International Conference on
Type
conf
DOI
10.1109/CoCoNet.2015.7411214
Filename
7411214
Link To Document