Title :
Influence of charge build-up on breakdown and wear-out in thin SiO2 layers on Si
Author :
M.W. Hillen;M.M. Heyns;S.K. Haywood;R.F. De Keersmaecker
Author_Institution :
ESAT laboratory, Katholieke Universiteit Leuven, Kardinaal Mercierlaan 94, B-3030 Heverlee, Belgium
fDate :
7/1/1983 12:00:00 AM
Abstract :
It has been suggested that breakdown of SiO2 layers on Si is preceded by injection and trapping of charge and by generation of trapping sites. For instance, generation of electron traps both in the bulk [1,2] and near the Si/SiO2 interface [3] during high-field stressing has been inferred from C-V and ramp I-V measurements. This data led to the present study, together with the fact that in short-channel MOSFET´s gate oxides must withstand electric fields, which are increased due to dimension scaling. For the first time accurate charge injection and sensing techniques were used before and after stresses at low and high fields, applied to thin thermally grown oxides on n- and p-type silicon.
Keywords :
"Silicon","Electron traps","Current measurement","Logic gates","Electric breakdown","Capacitance-voltage characteristics","Stress measurement"
Conference_Titel :
Conduction and Breakdown in Solid Dielectrics, Proceedings of First International Conference on
DOI :
10.1109/ICSD.1983.7411536