Design of low power CMOS RF building blocks

This paper overviews the implementation of CMOS radio-frequency (RF) building blocks intended for low power applications in the 2.4 GHz industrial, scientific, and medical (ISM) band. The design approach exploits the biasing of MOS devices in their moderate inversion region to optimize the trade-off between the performance and the power consumption. Two circuit structures are discussed. First, the cascade of a low-noise amplifier (LNA) and a mixer is presented that achieves a voltage gain of 31.4 dB, and a noise figure of 6.8 dB while consuming 360 μW. The second configuration is an LNA that is stacked with a voltage-controlled oscillator (VCO). It yields a gain of 18.3 dB, a NF of 3.2 dB and a phase noise of -119 dBc/Hz at 1 MHz offset from a power supply of 0.6 V while consuming 240 μW.