Low computational complexity digital pre-distortion for broadband power amplifiers

In this paper a novel approach is proposed for digital predistortion (DPD) with direct learning architecture (DLA) architecture to reduce the computational complexity. In PA behavioral models, the coefficients of volterra polynomial or simplified volterra polynomial are extracted from direct learning or indirect learning, which needs many hardware resources due to its matrix dimension and inverse operation in FPGA implementation. To speed up the computation and save hardware resource, we propose a novel method to use a constant matrix replace the time-varied input signal filled matrix based on stationary random process. To verify the proposed method, it was employed in PA linearization with a 40-MHz 2-carrier long term evolution (LTE) with class-AB GaN PA. Experimental results show that the proposed algorithm achieves almost same performance and convergence speed compared with traditional approach.