An architecture for a mode S secondary radar with all processing in software

This work presents a mode S secondary surveillance radar (SSR) architecture that enables signal processing to be done all in software. It avoids a widely implemented architecture approach with a first step of processing with a filter in hardware, normally implemented in FPGA. This proposed architecture replaces the hardware filter with a highly customized filter in software implemented in C language running as an operating system process executed with high priority. The filter in software keeps extracting preambles and payload from noise as hardware counterpart but on a CPU. The further processing steps of the mode S logic was implemented in high level language, simplifying project complexity and maintainability. To validate the architecture, a simulator was implemented with realistic constraints, and was tested with real data in the reception channel.