FEOL CMP modeling: Progress and challenges

Gate-last high-k metal gate technology introduced for the 45nm technology node added two new polishing steps in the front end of line (FEOL) flow: poly open polishing (POP) and Al replacement metal gate (Al RMG) chemical-mechanical polishing (CMP). For 20nm technology and below, even transistor gate height variation of only a few nanometers may lead to significant performance degradation of transistors. Modeling the POP and Al RMG CMP steps enables the study of systematic gate height variation caused by polishing impacts created by physical layout specifics, and the detection of hotspots. Although restricted design rules in the 20nm technology help improve the uniformity of a layout, they create difficulty in obtaining short-loop wafers for POP and Al RMG CMP steps. The new rules create additional challenges in designing and processing test chips for model building. However, there has been significant progress made in modeling FEOL CMP steps. This paper discusses FEOL CMP model building and hotspot detection challenges and progress, and presents some results of modeling.