DocumentCode :
3749889
Title :
Study on effect of back-surface treatment of silicon wafer in photo lithography process after CMP process
Author :
Ki Min; Sungmin Kang; Taesung Kim
Author_Institution :
Sungkyunkwan University, Suwon, South Korea
fYear :
2015
Firstpage :
1
Lastpage :
3
Abstract :
Recently design rule shrinkage of System LSI needs very tight process technology and leads to various types of pattern failure with photo lithography process conditions. One of pattern failure, called as local focus or focus spot is caused by particles attached to the back surface of the wafer. When wafer is mounted onto the chuck of a exposure equipment, it needs to be flat over a typical exposure area. If a particle is attached to the back surface of the wafer, it can cause patterning defocus by a localized height change. The Critical Dimension (CD) of the pattern may broaden locally or get distortion. This kinds of defect will result in pattern shorts or opens from the defective pattern to its neighbors. Most of the particles attached to the back side of wafer come from previous photo lithography process. We´ve found distinct increment focus spots after CMP process. So it is necessary to clean back surface particles before exposure process. In this study, we utilize Backside Surface Treatment (BST) process that provided from track equipment of Tokyo Electron Co., Ltd. By using BST process, we can get about 30% reduction of focus spots.
Keywords :
"Lead","Materials handling"
Publisher :
ieee
Conference_Titel :
Planarization/CMP Technology (ICPT), 2015 International Conference on
Type :
conf
Filename :
7411987
Link To Document :
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