DocumentCode :
3749907
Title :
Planarization limbo with silicon wafers
Author :
Dan Trojan;Marie Mitchel;Christopher Shumway;Paul Feeney
Author_Institution :
Axus Technology, 7001 W. Erie St. Suite 1, Chandler, AZ 85226, USA
fYear :
2015
Firstpage :
1
Lastpage :
3
Abstract :
An increasing number of substrates get sent through thinning. Some of those also require a polished surface. Temporary bonding is needed to support that. In order take some Si wafers down to 15u, a process flow with unique bonding, grinding, and polishing steps was used. Understanding how to improve many of the process steps was important to achieving the objective.
Keywords :
"Micromechanical devices","Bonding","Silicon","Polymers","Stress"
Publisher :
ieee
Conference_Titel :
Planarization/CMP Technology (ICPT), 2015 International Conference on
Type :
conf
Filename :
7412005
Link To Document :
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