• DocumentCode
    3749927
  • Title

    CMP solutions for 3D-NAND staircase CMP

  • Author

    Tina C. Li;Brian Reiss;Sudeep Pallikkara Kuttiatoor; Viet Lam; Jae-Dong Lee; Renhe Jia

  • Author_Institution
    Cabot Microelectronics Corporation, 870 N. Commons Drive, Aurora, IL 60504 USA
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    As NAND technology is moved from 2D to 3D, there are a few CMP steps to be newly added such as channel poly CMP and staircase (or ILD) CMP. Channel poly CMP is to polish many materials simultaneously such as SiN, oxide and poly-Si therefore it needs individual material rate tunability to meet final topography requirement. Staircase CMP process is identical to conventional ILD or IMD CMP but it needs high planarization efficiency (PE) and fast removal rate (RR) in order to meet higher step height and huge oxide removal amount. This study is to deal with slurries of 3D-NAND device integration having the rate tunability of various materials for channel poly and the high performance on PE and oxide rate for staircase CMP.
  • Keywords
    "Performance evaluation","Three-dimensional displays","Logic gates","Abrasives","Silicon compounds"
  • Publisher
    ieee
  • Conference_Titel
    Planarization/CMP Technology (ICPT), 2015 International Conference on
  • Type

    conf

  • Filename
    7412025