FPGA implementation of chaotic based AES image encryption algorithm

This paper describes the FPGA implementation of chaotic based advanced encryption standard (AES) using pipeline technique. The algorithm is a combination of chaotic maps and AES. In the proposed architecture, AES key is generated by chaotic maps and encryption is done by AES. The internal operations of each round of AES are optimized and parallel RAMs are used to implement the Sub-Bytes operation. Key expansion unit is synchronized with round unit which generate round key in each clock cycle. The key is stored and read from the key RAM in the same clock cycle which increases the speed. The proposed architecture is implemented using Verilog HDL and Xilinx ISE Design Suite 14.5. Implementation results are compared with previously reported pipelined AES architectures on same FPGA devices. The comparison results show that our proposed architecture is efficient in terms of speed and area.