Title :
Investigation of the internal noises in the chip with orthogonal topology of power supply feeding
Author_Institution :
Inst. of Comput. Informational Technol., Temopil Acad. of Nat. Economy, Ternopil, Ukraine
Abstract :
In this paper the author has considered conductive noise caused by simultaneous switching of logic gates as the main internal noise in the chip. Earlier, the mathematical models of conductive noise for different types of power supply feeding have been developed. Analysis of them has shown that the value and the shape of the noise voltage distribution depend on the technological and constructive parameters of the power supply lines. In this article the author has investigated the mathematical model of conductive noise in the matrix chip with orthogonal topology of power supply feeding. The obtained results can be used to estimate the most critical area of the chip from the viewpoint of influence of internal noises, to make the recommendation for developing the special type of topology as well as for another reasons
Keywords :
VLSI; electromagnetic interference; logic gates; power supplies to apparatus; switching; EMC; chip internal noises; conductive noise; equivalent circuit; logic gates switching; mathematical models; matrix VLSI; matrix chip; noise voltage distribution shape; orthogonal topology; power supply feeding; simultaneous switching; Electromagnetic interference; Grounding; Logic gates; Mathematical model; Noise shaping; Power supplies; Shape; Topology; Transmission line matrix methods; Very large scale integration;
Conference_Titel :
Electromagnetic Compatibility, 2001. EMC. 2001 IEEE International Symposium on
Conference_Location :
Montreal, Que.
Print_ISBN :
0-7803-6569-0
DOI :
10.1109/ISEMC.2001.950727
