A 6-bit phase shifter with low RMS phase error and flat gain across 1.9–2.6GHz

This paper presents a 6-bit phase shifter with a low root-mean-square (RMS) phase error and a flat gain across 1.9-2.6GHz. An input balun which utilizes a differential signal correction system consisting of two capacitor-cross-coupled (CCC) pairs and one CCC buffer is realized to ensure good phase and amplitude balance. Based on the relationship of the W/L of DAC cells, an encode rule which makes the 6-bit input generate eight DAC code is presented. A gain compensation technique is employed to realize a flat overall gain in the range of 1.9-2.6GHz. In 0.18-μm CMOS technology, the simulation results illustrate that the proposed phase shifter achieves less than 0.635 degree RMS phase error and less than 0.6dB gain variation across 1.9-2.6GHz.