Title :
Novel symmetrical buffer design for VLSI applications
Author :
Chow, Hwang-Cherng ; Feng, Wu-Shiung
Author_Institution :
Dept. of Electron. Eng., Chang Gung Univ., Tao-Yuan, Taiwan
Abstract :
Novel fast buffers by transient part circuit technique are described in this paper. The proposed circuits are fully symmetrical in its structure, therefore design is straight forward and well balanced speed is easily obtained. As compared to prior arts, the delay ratio of this work is over 300% and 10% balance improvement, respectively. While based on a design criterion of the same area the proposed buffer shows 27% and 76% averaged speed enhancements on propagation delays
Keywords :
VLSI; buffer circuits; integrated circuit design; VLSI circuit; propagation delay; symmetrical buffer design; transient part circuit technique; Art; Circuits; Clocks; Logic design; Logic devices; Low voltage; MOSFETs; Propagation delay; Switches; Very large scale integration;
Conference_Titel :
Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
Conference_Location :
Lansing, MI
Print_ISBN :
0-7803-6475-9
DOI :
10.1109/MWSCAS.2000.951614
