• DocumentCode
    375073
  • Title

    A new logic transformation method for both low power and high testability

  • Author

    Son, Yoon-Sik ; Chong, Jong-Wha

  • Author_Institution
    Dept. of Electron. Eng., Hanyang Univ., Seoul, South Korea
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    332
  • Abstract
    In this paper, a new logic transformation method to achieve both low power consumption and high testability is proposed. Our method is based on the redundancy insertion approach. We also describe the structure of redundant connections that operate as test points in the test mode. The results of experiments on MCNC benchmark circuits show that the transformed circuit consumes less power in the normal mode and has higher testability in the test mode than the original circuit
  • Keywords
    logic design; logic testing; low-power electronics; redundancy; logic transformation; low-power design; redundancy insertion; testability; Benchmark testing; Circuit testing; Clocks; Energy consumption; Logic circuits; Logic testing; Parasitic capacitance; Power dissipation; Power engineering and energy; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
  • Conference_Location
    Lansing, MI
  • Print_ISBN
    0-7803-6475-9
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2000.951654
  • Filename
    951654