A RNS-based matrix-vector-multiply FCT architecture for DCT computation

Author

Fernandez, P.G. ; García, A. ; Ramírez, J. ; Parrilla, L. ; Lloris, A.

Author_Institution

Dept. of Electr. Eng., Jaen Univ., Spain

Volume

1

fYear

2000

fDate

2000

Firstpage

350

Abstract

A Field-Programmable Logic (FPL) implementation of the Discrete Cosine Transform (DCT) based on the Residue Number System (RNS) is presented. It uses a combination of the Fast Cosine Transform (FCT) algorithm and the matrix-vector multiplication (MVM). This paper shows that the RNS-based FCT-MVM implementation provides a throughput improvement over the equivalent binary system up to 72%, while its advantage over the binary distributed arithmetic implementation is up to 128%

Keywords

digital signal processing chips; discrete cosine transforms; field programmable gate arrays; matrix algebra; multiplying circuits; residue number systems; DSP arithmetic; RNS-based FCT-MVM implementation; discrete cosine transform; fast cosine transform algorithm; field-programmable logic implementation; matrix-vector multiplication; residue number system; throughput improvement; Arithmetic; Computer architecture; Decorrelation; Digital signal processing; Discrete cosine transforms; Discrete transforms; Dynamic range; Hardware; Matrix decomposition; Signal processing algorithms;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951658

Filename

951658