A 65 nm CMOS +14 dBm-Psat and 10%-PAE 81–86 GHz power amplifier with parallel combiner

This paper presents an 81-86 GHz E-band power amplifier fabricated with 65 nm CMOS process. A passive splitter is designed to transfer a pair of differential signal into two pairs of differential signals and satisfy phase requirement of output parallel power combiner. A substitution method is presented to trade off the simulation time and accuracy while using EM simulator to characterize the MOS transistor´s access lines with stacked via arrays. The proposed PA achieves 9.5 dBm P_1-dB, 14.16 dBm P_SAT and 21.5 dB maximum power gain at 83.5 GHz. The PAEs at P_1-dB and P_SAT are 3.6% and 10.13% respectively.