• DocumentCode
    375083
  • Title

    Timing analysis of block replacement algorithms on disk caches

  • Author

    Rajamoni, Ramakrishnan ; Bhagavathula, Ravi ; Pendse, Ravi

  • Author_Institution
    Dept. of Electr. Eng., Wichita State Univ., KS, USA
  • Volume
    1
  • fYear
    2000
  • fDate
    2000
  • Firstpage
    408
  • Abstract
    Cache memories are used to reduce the memory latency in systems. While instruction references of a CPU exhibit high temporal and spatial locality, disk references exhibit very minimal temporal and spatial locality. Owing to the fact that most of the block replacement algorithms exploit the available locality to improve cache performance, they are more effective with CPU instruction caches than with disk caches. This paper presents the results of an investigation of cache write policies and the impact of the Least Recently Used (LRU) and the Segmented LRU (SLRU) block replacement algorithms on the performance of disk caches. To obtain optimal performance at all workloads and cache sizes, an adaptive write caching policy is introduced. The adaptive write caching policy does a dynamic selection of the write policy at run time. Simulations reveal that when the cache size is less than 2 MB, caches employing adaptive write caching policy are 17% faster over caches employing write-back policy. For cache sizes of 16 MB and above the performance improvement is 9%. The performance improvement of caches employing adaptive write caching policy over caches employing write-through policy is 2.65% for cache sizes of 2 MB and is 27%, for cache sizes of 16 MB and above. The adaptive write caching policy yields optimum performance for many of the disk workloads and disk cache sizes
  • Keywords
    cache storage; disc storage; storage allocation; timing; 2 to 16 MB; LRU block replacement algorithms; adaptive write caching policy; cache memories; cache write policies; disk caches; dynamic selection; least recently used block replacement algorithms; memory latency; optimal performance; segmented LRU block replacement algorithm; timing analysis; Algorithm design and analysis; Cache memory; Delay; Fabrication; Hard disks; Random access memory; Solid state circuits; System performance; Timing; Writing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on
  • Conference_Location
    Lansing, MI
  • Print_ISBN
    0-7803-6475-9
  • Type

    conf

  • DOI
    10.1109/MWSCAS.2000.951670
  • Filename
    951670