A low power architecture for a new efficient block-matching motion estimation algorithm

Author

Mahmoud, Hanan A. ; Bayoumi, Magdy A. ; Wilson, Beth

Author_Institution

The Center for Adv. Comput. Studies, Univ. of Louisiana, Lafayette, LA, USA

Volume

1

fYear

2000

fDate

2000

Firstpage

436

Abstract

This paper presents an exhaustive search algorithm for block matching motion estimation. The proposed algorithm reduces the computational load with successive elimination of non-candidate blocks in the search window. The proposed algorithm locates the global optima as located by the full search block-matching algorithm. This computational reduction leads to low-power VLSI implementation of the algorithm.. Also, it leads to faster efficient motion estimation procedure. The correctness of this algorithm and its complexity presented. Simulation results on benchmark video clips are presented

Keywords

VLSI; digital signal processing chips; image matching; low-power electronics; motion estimation; search problems; block matching motion estimation; computational load; exhaustive search algorithm; global optima; low-power VLSI architecture; Circuit testing; Computational complexity; Computational modeling; Computer architecture; Distortion measurement; Energy consumption; Equations; Motion estimation; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2000. Proceedings of the 43rd IEEE Midwest Symposium on

Conference_Location

Lansing, MI

Print_ISBN

0-7803-6475-9

Type

conf

DOI

10.1109/MWSCAS.2000.951677

Filename

951677