A leakage tolerant true single-phase clock dual-modulus prescaler scheme

A new leakage-tolerant true single-phase clock dual-modulus prescaler based on a stage-merged scheme is presented. Leakage-restricting transistors are used to reduce the leakage currents at critical nodes and leakage-related malfunctions are eliminated at minimal cost in terms of speed, power and area overheads. An HSPICE simulation in a 40 nm process shows that the proposed divide-by-2/3 divider can effectively enhance robustness against leakage currents to extend the low frequency limit of the circuit over wide temperature and threshold voltage ranges. Additionally, the proposed design shows speed and power performance that is comparable to the performance levels of referenced designs.