DocumentCode :
3752111
Title :
An efficient VLSI architecture for discrete wavelet transform
Author :
Chih-Hsien Hsia;Jia-Hao Yang;Weihua Wang
Author_Institution :
Department of Electrical Engineering, Chinese Culture University, Taipei, Taiwan
fYear :
2015
Firstpage :
684
Lastpage :
687
Abstract :
A Lifting-based Discrete Wavelet Transform (DWT) is a time/frequency analysis conversion method that is often used in JPEG2000 image compression systems. Its filter bank has a dual-mode base function that consists of coefficients of 9/7 and 5/3. Generally, in the process of realizing Very Large Scale Integration (VLSI) architecture, there is a longer critical paths and increased cost of hardware, so paper proposes a folding and pipelined architecture to solve the problems in VLSI architecture design; In order to solve the problem of a large area of hardware due to the excessive use of the multipliers in dual-mode operation, a shifter-adder-multiplier architecture and dual-mode filter architecture are combined. The experimental results show that the hardware architecture proposed in this work has a short critical path. The hardware supports dual-mode hardware wavelet coefficients, decrease latency, and multiplierless, and more suitable for VLSI to implement and apply in low cost JPEG2000 compression systems.
Keywords :
"Computer architecture","Hardware","Very large scale integration","Filter banks","Discrete wavelet transforms","Adders","Wavelet coefficients"
Publisher :
ieee
Conference_Titel :
Signal and Information Processing Association Annual Summit and Conference (APSIPA), 2015 Asia-Pacific
Type :
conf
DOI :
10.1109/APSIPA.2015.7415359
Filename :
7415359
Link To Document :
بازگشت