Title :
A Method to Search Fallible Branch in FPGA Programs
Author :
Haixu Li;Yunyi Yan;Baolong Guo
Author_Institution :
Sch. of Aerosp. Sci. &
Abstract :
This paper discusses about a method to find the fallible branch in FPGA programs using VHDL, the method includes finding the topological relation between entities using VHDL grammar, modeling the topological relation into a distance matrix and finding the shortest route using ACO. The shortest route is the fallible branch.
Keywords :
"Field programmable gate arrays","Ports (Computers)","Grammar","Error probability","Presses","Optimization","Circuit synthesis"
Conference_Titel :
Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP), 2015 International Conference on
DOI :
10.1109/IIH-MSP.2015.75