DocumentCode :
3752584
Title :
Flash fast-locking digital PLL using LT SPICE
Author :
Mahmoud Fawzy Wagdy;Syed Zeeshan Ahmed Kabeer
Author_Institution :
Electrical Engineering, California State University, Long Beach (CSULB), 1250 Bellflower Blvd., 90840, USA
fYear :
2015
Firstpage :
229
Lastpage :
234
Abstract :
A flash fast-locking digital phase-locked loop (DPLL) is presented using transistor level 50 nm CMOS technology and 1V power supply in LT SPICE. The DPLL operation includes two stages: (1) a coarse-tuning stage for frequency tracking which employs a flash algorithm similar to the one employed in flash A/D converters (ADCs) and (2) a fine-tuning stage similar to conventional (classical) DPLLs. The coarse-tuning stage consists of frequency comparator array, a priority encoder, a digital-to-analog converter (DAC), and control logic (CL). Design considerations and implementations are presented in this paper. The fast-locking flash DPLL reduces the lock time by a factor of about 2.19 when compared with the conventional DPLL counterpart, in the frequency range 80 MHz-1.1 GHz.
Keywords :
"Voltage-controlled oscillators","Voltage control","CMOS integrated circuits","CMOS technology","Computational modeling","SPICE","Manuals"
Publisher :
ieee
Conference_Titel :
Computer Engineering Conference (ICENCO), 2015 11th International
Type :
conf
DOI :
10.1109/ICENCO.2015.7416353
Filename :
7416353
Link To Document :
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