Hard block reduction and synthesis improvements in Odin II

A Field-Programmable Gate Array (FPGA) is an integrated circuit that allows users to program product features and functions after manufacturing. Verilog-to-Routing (VTR) is an open source CAD tool for conducting FPGA architecture and CAD research and development. As one of the core tools of VTR, Odin II is responsible for Verilog elaboration and hard block synthesis. This project describes the improvements in Odin II on three aspects: for loop support, abstract syntax tree (AST) simplification and hard block reduction. This work allows elaboration of a for loop statement by modifying the Abstract Syntax Tree (AST). There are different alternatives to simplify an AST, and this paper demonstrates three ways: simplifying expressions with variables, reducing parameters with values and using shift operations to replace multiplications or divisions. For a circuit design, some hard blocks in the netlist have the same high-level function. This project further provides a method to reduce redundant hard blocks. Each implementation is tested with designed testing cases or sets of benchmarks, and the results of running them through Odin II and VTR are demonstrated.