A consideration of signal frequency detector in digital peak current mode dc-dc converter

The purpose of this paper is to reveal the designing of the static characteristic of the digital peak current mode dc-dc converter using a voltage controlled oscillator (VCO). In the proposed method, it is able to sample the reactor current by using the VCO and the delay circuit. The improvement of the dynamic characteristic and the analysis of the proposed method have already been revealed. However the design method in the static characteristic of the proposed method has not been clear. In this paper, the analysis about the resolution of the output voltage is revealed for the designing of the proposed method in static characteristic. The change of the output voltage against the change of the delay time in the signal frequency detector is confirmed by comparing the analysis result and simulation results. Furthermore, the effect, which the signal frequency detector gives to the output voltage in the transient state, is discussed.