Active current mirror receiver

Describes a current-mode I/O transceiver designed for use in chip-to-chip communications, which employs an active current mirror in the receiver to recover the data and terminate the transmission line to its characteristic impedance. The circuit was designed to require little headroom, so that it would be appropriate for future CMOS processes in which transistor thresholds are scaled more slowly than supply voltage. A feedback circuit was designed to compensate for variations in process parameters and supply voltage; it adjusts the receiver´s bias voltages so that the clock output has a 50% duty cycle. A prototype circuit was designed in the 5V, 0.5-μm HP-CMOS14B process, and fabricated through the MOSIS Service. Measured results indicate that the receiver can support data rates of 910 Mb/s/pin using a transmitted current pulse of 598 μA, while dissipating 6 mW of power from a 2.5-V supply. With the dynamic biasing network enabled, the receiver operated properly over a supply range of 2.25 to 3 V. With a 3-V supply, the receiver was capable of 1.02 Gb/s/pin bandwidth with a power dissipation of 9 mW